Computer Architecture
AI has not changed what a processor is, but it has changed which parts of the machine decide performance: tensor and NPU datapaths, reduced-precision arithmetic, and memory bandwidth now drive industry hardware decisions, and low-level code is increasingly drafted by AI tools that a human must verify against the actual datapath. The course keeps its hardware identity and adds accelerator organization, measured performance analysis, and verification of machine-generated assembly and intrinsics.
Current catalog prerequisites — (CSC 200 or 2000).
Current description → proposed description
This course investigates the internal hardware function and structure of a computer in depth. The programmer’s relationship to architecture and the computer scientist’s relationship to organization are studied. Major topics include: peripherals (I/O and storage), the processor (CPU and memory), ALU (computer arithmetic), and the CU (computer instruction sets). Students will construct computer circuits from component chips and carry out programming assignments in assembly language.
Prerequisites: (CSC 200 or 2000).
Computer Architecture examines the internal structure and function of computing systems and the relationship between hardware organization and the software that runs on it. Core topics include instruction set architecture and assembly programming, the processor datapath and control unit, computer arithmetic and the ALU, the memory hierarchy, storage, and input/output. Students construct circuits from component chips and write assembly-language programs, among them a quantized dot-product inner loop, so that abstract machine models are grounded in physical behavior. The course extends this foundation to the accelerator-centric machines now standard in industry: GPU and NPU tensor datapaths, reduced-precision numeric formats, and the memory-bandwidth and data-movement limits that govern the latency, cost, and energy of inference workloads. Students measure real programs against roofline and cache models, test whether observed performance matches architectural claims, and document their review of low-level artifacts generated by AI coding tools. Energy, cost, and access consequences of compute decisions are treated as engineering responsibilities rather than externalities.
What changes
- GPU/NPU tensor datapaths and reduced-precision formats
- Memory bandwidth and roofline analysis of data movement
- Measured benchmarking against architectural claims
- Verification of AI-generated assembly and intrinsics
- Energy and compute-resource stewardship
6 proposed outcomes, mapped to 7 program outcomes
Each outcome below is written to be observable and assessable, and each is mapped to the program learning outcomes for which it produces evidence.
Students will be able to construct digital circuits and datapath components from logic primitives that correctly realize the arithmetic, control, and register-transfer operations of a simple processor, and evaluate that design against a specified computational workload.
Both halves of PLO 4.2 are in the outcome itself: the student proposes a working datapath built from primitives and then evaluates that specific design against a stated workload, and the substrate reading under which this hardware course claims an AI-solution PLO is set out once in the notes rather than asserted here.
Students will be able to implement assembly-language programs that exercise a processor's instruction set, addressing modes, register file, and memory model, including a quantized dot-product inner loop.
Hand-implementing the quantized dot-product kernel that accelerators execute is a proposed solution the student must then make work under real machine constraints, supplying PLO 4.2's propose-and-evaluate evidence on the substrate AI workloads actually run on (see notes for the substrate reading).
Students will be able to analyze the effect of the memory hierarchy, storage, and I/O interconnect bandwidth on program performance using measured cache, latency, and roofline data, including an inference workload.
Drawing conclusions from measured cache, latency, storage, and interconnect data for an inference workload is quantitative analysis of AI performance patterns (PLO 6.2), and explaining what those measurements reveal about that workload's behavior on the machine is the interpretation of AI data outcomes PLO 6.1 names.
Students will be able to differentiate accelerator architectures, including GPU and NPU tensor datapaths and reduced-precision numeric formats, by their compute and data-movement characteristics for a given workload and by the deployment cost and access consequences of choosing each.
Separating accelerators by their measured throughput and bandwidth characteristics requires interpreting and explaining AI hardware performance data (PLO 6.1), and weighing the deployment cost and access consequences of each choice is exactly the critical analysis of data-driven outcomes together with their societal impact that PLO 4.1 requires.
Students will be able to critique low-level artifacts produced by AI coding assistants, such as assembly routines or intrinsics, for functional correctness, timing, and efficiency on the target architecture, documenting the verification approach applied and what evidence would have changed the reviewer's judgment.
Documenting the verification approach applied and naming the evidence that would have changed the judgment is self-assessment of the student's own problem-solving process, which is the reflective evidence PLO 4.3 measures, while critiquing the assistant's output for correctness rather than accepting it is the critical analysis of a machine-produced outcome PLO 4.1 names.
Students will be able to evaluate competing hardware configurations by energy and cost per unit of computation, including who bears the resulting energy and cost burden.
Quantifying energy and cost per unit of computation is concrete evidence of the responsible resource management PLO 2.3 requires, and determining who bears the resulting burden is the assessment of fairness and moral impact PLO 6.3 names.
Program outcomes this course reaches
Filled cells are program learning outcomes with at least one supporting course learning outcome in this course. Sparse coverage is expected — no single course carries all eighteen.